Variants
Variants are a feature unique to the Packtype custom grammar (.pt files), and
allow definitions to be varied based on conditions presented to the parser. This
mechanism can be useful to allow different parts of a large project to operate
at different cadences while referring to a central set of definitions - by
allowing changes to be 'gated' on specific conditions, different consumers can
take updates at their own pace.
Example
The example below shows how variants can be used to encapsulate two different sizings for a bus, while common definitions can exist in just a single location:
If this was rendered to SystemVerilog without providing any variant conditions, then the output would look like:
While if you were to provide NARROW_BUS as a condition:
Note
While this example only shows constants being declared, any type, constant,
or enum declaration can be made within a variants block just as if it was
a native part of the package.
Default Variant
A variants block must specify a default that is taken whenever no other condition
matches. If a variants block does not specify a default, then a TransformerError
will be raised during the parsing process.
Only a single default may be specified per variants block, specifying more than
one default will cause a VariantError to be raised.
Variant Conditions
Variant entries can use and / or keywords to create more complex statements,
these follow the same operator precedence as Python (and evaluated first,
followed by or).
Where multiple conditions match, only the first variant block is considered.
For example:
This means that where:
COND_AandCOND_Bare provided then ONLYX = 1will be evaluated;COND_Ais provided then ONLYY = 2will be evaluated;- In any other scenario ONLY
Z = 3will be evaluated.